1. Field of Invention
The present invention relates to a liquid crystal display (LCD) panel, and more particularly to a wiring structure of an LCD panel, which has a double metal layer structure and is capable of reducing wiring impedance.
2. Related Art
In currently known technologies, as for display devices employing a Chip On Film (COF) technology, the metal wiring employing the COF technology has a higher impedance than that of conventional devices using a printed wiring board (PWB) for signal transmission, so that when the COF wiring impedance is high, the mura problem of tape automated bonding (TAB) easily occurs, thereby affecting the quality of the panel. In order to reduce the wiring impedance, a double-layer metal wiring structure is used.
FIG. 1 is a top view of a double-layer metal wiring structure in the prior art. FIG. 2 is an equivalent circuit diagram of the double-layer metal wiring structure in the prior art. FIG. 3A is a cross-sectional view of the double-layer metal wiring structure in the prior art, taken along Line A-A. FIG. 3B is a cross-sectional view of the double-layer metal wiring structure in the prior art, taken along Line B-B. Referring to FIGS. 1, 2, 3A, and 3B, since a signal needs to pass through a double-layer metal wiring structure 5 (formed on a glass substrate 50), the signal needs to be transmitted to a source/drain electrode layer 52 through an indium tin oxide (ITO) layer 54, such that a gate electrode layer 51 and the source/drain electrode layer 52 can transmit the COF signals at the same time. Definitely, an insulating layer 53 is completely or partially formed between the gate electrode layer 51, the source/drain electrode layer 52, and the ITO layer 54, so as to provide electrical insulation there-between.
For example, in the double-layer metal wiring structure 5, when a signal of a source integrated circuit (IC) 61 is transmitted by the gate electrode layer 51, the signal needs to be transmitted to a gate IC 62 through an impedance R1 of the ITO layer and the gate electrode layer, an impedance R2 of the gate electrode layer, and the impedance R1 of the gate electrode layer and the ITO layer, that is, along a direction represented by Arrow D; and when the signal is transmitted by the source/drain electrode layer 52, the signal needs to be transmitted to the gate IC 62 through an impedance R3 of the ITO layer, an impedance R4 of the ITO layer and the source/drain electrode layer, an impedance R5 of the source/drain electrode layer, the impedance R4 of the source/drain electrode layer and the ITO layer, and the impedance R3 of the ITO layer, that is, along a direction represented by Arrow C (as shown in FIG. 2).
Since the signal must be conducted to the double-layer metal, the ITO layer 54 is additionally used as a jump layer for conducting the signal on the gate electrode layer 51 to the source/drain electrode layer 52, thereby transmitting the signal through the double-layer metal.
However, since the ITO layer 54 has a high impedance, that is, the impedance of the ITO layer 54 is about 80 times of that of aluminum, the signal loss occurs when the signal on the gate electrode layer 51 is transmitted to the source/drain electrode layer 52, resulting in that the original signal cannot be kept intact after being transmitted through the double-layer metal.